Senior Digital Verification Engineer

• Freelance or contracting

• Only professionals living in the Netherlands

• 12 months starting ASAP

• 3 days in the office weekly in Eindhoven

• Must haves: a minimum of 8 years in specific Digital Verification, communication, independence and structure

The assignment

A leading global semiconductor company in Eindhoven is seeking multiple experienced design engineer to carry out a variety of assignments related to semiconductor device design and verification. The role involves designing and reviewing chip layouts, performing circuit checks, preparing and updating specifications, and assessing semiconductor components and devices. This engineer will interpret product requirements and logic diagrams to define devices, and will typically manage projects or parts of projects focused on the design, verification, modification, and evaluation of semiconductor hardware. Additionally, the role includes conducting experimental testing, analyzing results, developing technical specifications for component selection, and, when needed, assessing vendor capabilities to support development activities. A strong focus is placed on design verification.

Key Responsibilities

• Take ownership of pre-silicon verification for IP modules, IP subsystems, and/or the SoC top level.

• Define the digital verification strategy and develop verification plans for the SoC or its sub-blocks.

• Collaborate closely with hardware, firmware, and software design teams, as well as with architecture and systems engineering, to fully understand the functional and application requirements of the IP subsystems and the complete SoC.

• Execute the verification plan in alignment with product specifications and requirements provided by the product architects.

• Develop, debug, and execute verification environments using C/C++, SystemVerilog, or UVM for RTL/netlist simulations.

• Design and implement test cases within the appropriate verification frameworks, generate stimulus and assertions, perform simulations, debug test cases on various design models (including RTL, power-aware RTL, gate-level netlists, FPGA prototypes, or emulation platforms), run regressions, and gather and analyze code and functional coverage metrics.

Required Qualifications

• A bachelor’s degree or higher in Microelectronics, Electronics, Electrical Engineering, Computer Science, or a related field, combined with 8–12 years of relevant experience.

• Solid understanding of SoC architectures and their operational principles.

• Proven knowledge of both directed and constrained-random verification methodologies.

• Proficiency in UVM, Verilog, SystemVerilog, C/C++, and shell scripting.

• Strong programming capabilities are essential.

• Familiarity with scripting languages such as Perl, TCL, or Python is considered an advantage.

• Effective communication skills and the ability to collaborate with international teams while working independently.